hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 32

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

A0 is used for DLL enable or disable. A1 is used for
enabling half-strength data-output driver. A2 and A6
enables On-Die termination (ODT) and sets the Rtt
value. A[5:3] are used for additive latency settings and
A[9:7] enables the OCD impedance adjustment mode.
A10 enables or disables the differential DQS and
RDQS signals, A11 disables or enables RDQS.
3.7
The DLL must be enabled for normal operation. DLL
enable is required during power up initialization, and
upon returning to normal operation after having the DLL
disabled. The DLL is automatically disabled when
entering Self-Refresh operation and is automatically re-
enabled and reset upon exit of Self-Refresh operation.
3.8
Under normal operation, the DRAM outputs are
enabled during Read operation for driving data (Qoff bit
in the EMR(1) is set to 0). When the Qoff bit is set to 1,
the DRAM outputs will be disabled. Disabling the
3.9
Table 10
RDQS, RQDS which can be programmed by A[11:10]
address bits in EMRS. RDQS and RDQS are available
Table 10
EMRS(1)
A11
(RDQS Enable)
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
3.10
The Extended Mode Registers EMR(2) and EMR(3)
are reserved for future use and must be programmed
when setting the mode register during initialization.The
extended mode register EMR(2) is written by asserting
LOW on CS, RAS, CAS, WE, BA0 and HIGH on BA1,
while controlling the states of the address pins. The
DDR2 SDRAM should be in all bank precharge with
Data Sheet
lists all possible combinations for DQS, DQS,
DLL Enable/Disable
Output Disable (Qoff)
Single-ended and Differential Data Strobe Signals
Single-ended and Differential Data Strobe Signals
Extended Mode Register EMR(2)
A10
(DQS Enable)
0 (Enable)
1 (Disable)
0 (Enable)
1 (Disable)
DM
DM
RDQS
Strobe Function Matrix
RDQS/DM
RDQS
Hi-Z
Hi-Z
RDQS
RDQS
Hi-Z
33
Address bit A12 have to be set to 0 for normal
operation. With A12 set to 1 the SDRAM outputs are
disabled and in Hi-Z. 1 on BA0 and 0 for BA1 have to
be set to access the EMRS(1). A13 and all “higher”
address bits have to be set to 0 for compatibility with
other DDR2 memory products with higher memory
densities. Refer to Extended Mode Register Definition.
Any time the DLL is reset, 200 clock cycles must occur
before a Read command can be issued to allow time for
the internal clock to be synchronized with the external
clock. Failing to wait for synchronization to occur may
result in a violation of the
DRAM outputs allows users to measure
during Read operations, without including the output
buffer current and external load currents.
in ×8 components only. If RDQS is enabled in ×8
components, the DM function is disabled. RDQS is
active for reads and don’t care for writes.
CKE already high prior to writing into the extended
mode register. The mode register set command cycle
time (t
operation to the EMR(2). Mode register contents can
be changed using the same command and clock cycle
requirements during normal operation as long as all
banks are in precharge state.
DQS
DQS
DQS
DQS
DQS
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
MRD
) must be satisfied to complete the write
DQS
DQS
Hi-Z
DQS
Hi-Z
512-Mbit DDR2 SDRAM
Signaling
differential DQS signals
single-ended DQS signals
differential DQS signals
single-ended DQS signals
t
AC
or
Functional Description
09112003-SDM9-IQ3P
t
DQSCK
Rev. 1.6, 2005-08
parameters.
I
DD
currents