hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 68

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Figure 54
Notes
1. Device must be in the “All banks idle” state before
2.
3.25
Power-down is synchronously entered when CKE is
registered LOW, along with NOP or Deselect
command. CKE is not allowed to go LOW while mode
register or extended mode register command time, or
read or write operation is in progress. CKE is allowed to
go LOW while any other operation such as row
activation, Precharge, Auto-Precharge or Auto-Refresh
is in progress, but power-down
be applied until finishing those operations.
The DLL should be in a locked state when power-down
is entered. Otherwise DLL should be reset after exiting
power-down mode for proper read operation. DRAM
design guarantees it’s DLL in a locked state with any
CKE intensive operations as long as DRAM controller
complies with DRAM specifications.
If power-down occurs when all banks are precharged,
this mode is referred to as Precharge Power-down; if
power-down occurs when there is a row active in any
bank, this mode is referred to as Active Power-down.
Data Sheet
ODT
CMD
CKE
CK/CK
entering Self Refresh mode.
t
Read with Auto-Precharge command.
XSRD
T0
(
≥
200
Self Refresh Timing
Power-Down
t
CK
tis
T1
) has to be satisfied for a Read or a
T2
tAOFD
I
DD
specification will not
T3
tRP
Self Refresh
tis
Entry
T4
CK/CK may
be halted
69
tCKE
T5
3. t
4. Since CKE is an SSTL input,
For Active Power-down two different power saving
modes can be selected within the MRS register,
address bit A12. When A12 is set to LOW this mode is
referred as “standard active power-down mode” and a
fast power-down exit timing defined by the
parameter can be used. When A12 is set to HIGH this
mode is referred as a power saving “low power active
power-down mode”. This mode takes longer to exit
from the power-down mode and the
parameter has to be satisfied.
Entering power-down deactivates the input and output
buffers, excluding CK, CK, ODT and CKE. Also the DLL
is disabled upon entering Precharge Power-down or
slow exit active power-down, but the DLL is kept
enabled during fast exit active power-down. In power-
down mode, CKE LOW and a stable clock signal must
be maintained at the inputs of the DDR2 SDRAM, and
all other input signals are “Don’t Care”. Power-down
duration is limited by 9 times
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
Read or a Read with Auto-Precharge command
maintained during Self Refresh.
XSNR
CK/CK must
be stable
has to be satisfied for any command except a
tis
>= tXSNR
Tm
NOP
512-Mbit DDR2 SDRAM
>=tXSRD
Command
Non-Read
t
Tn
REFI
Functional Description
09112003-SDM9-IQ3P
V
of the device.
REF
Rev. 1.6, 2005-08
must be
t
XARDS
Command
t
Read
XARD
Tr
timing
timing