hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 33

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 11
Field
BA2
BA1
BA0
A
SRF
A
1) w = write only
3.11
The Extended Mode Register EMR(3) is reserved for
future use and all bits except BA0 and BA1 must be
programmed to 0 when setting the mode register during
Data Sheet
Bits
16
15
14
[13:8]
[7]
[6:0]
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010
Extended Mode Register EMR(3)
Type
reg.addr
w
w
w
1)
Description
Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
0
Bank Adress[1]
1
Bank Adress[0]
0
Address Bus[13:8]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0
Address Bus[7]
Note: When DRAM is operated at 85 °C £ T
0
1
Address Bus[6:0]
0
B
B
B
B
B
B
B
BA2, Bank Address
BA1, Bank Address
BA0, Bank Address
A[13:8], Address bits
must be enabled by setting bit A7 to "1" before the self refresh mode can be
entered.
A7, disable
A7, enable, adapted self refresh rate for TCASE > 85 °C
A[6:0], Address bits
34
initialization. The EMRS(3) is written by asserting low
on CS, RAS, CAS, WE, BA2 and high on BA0 and BA1,
while controlling the state of the address pins.
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
CASE
< 95 °C the extended self refresh rate
512-Mbit DDR2 SDRAM
Functional Description
09112003-SDM9-IQ3P
B
)
Rev. 1.6, 2005-08