hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 71

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Figure 58
WL = 2, WR = 3, BL = 4
Note: Active Power-Down mode exit timing
Figure 59
Note: "Precharge" may be an external command or an internal precharge following Write with AP.
Data Sheet
D Q S ,
D Q S
C K , C K
C K E
C M D
D Q
CK, CK
CKE
CMD
state in the MR, address bit A12. WR is the programmed value in the MRS mode register.
T0
W R IT E
w /A P
Precharge
T0
WL = RL - 1 = 2
Active Power-Down Mode Entry and Exit Example after a Write Command with AP
Precharge Power Down Mode Entry and Exit
T1
N O P
Power-Down
Precharge
tIS
Entry
T1
NOP
tRP
DIN A0 DIN A1 DIN A2 DIN A3
T2
N O P
T2
NOP
T3
N O P
WL + BL/2 + WR
T4
t
N O P
XARD
T3
NOP
(“fast exit”) or
T5
N O P
WR
72
NOP
T6
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
N O P
Power-Down
Precharge
t
XARDS
tIS
Power-Down
Tn
Exit
NOP
Active
Entry
tIS
T7
(“slow exit”) depends on the programmed
N O P
Tn+1
tXP
NOP
N O P
Power-Down
512-Mbit DDR2 SDRAM
Active
Exit
Tn+2
Tn
Command
N O P
Valid
tIS
Functional Description
09112003-SDM9-IQ3P
Tn+1
tXARD or
tXARDS *)
Rev. 1.6, 2005-08
N O P
NOP
Act.PD 3
Tn+2
C o m m a nd
V a lid