tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 10

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.2
P00~P07
AD0~AD7
P10~P17
AD8~AD15
A8~A15
P20~P27
A0~A7
A16~A23
P30
RD
P31
WR
P32
HWR
P33
WAIT
P34
BUSRQ
P35
BUSAK
P36
R/W
P37
DSU
P40
CS0
P41
CS1
P42
CS2
P43
CS3
P44
SCOUT
P50~P57
AN0~AN7
ADTRG
P60~P67
AN8~AN15
KEY0-KEY7
P90
DSU (DCLK)
KEY8
Pin Name # of Pins
Pin Usage Information
Table 2.2.1 lists the names and functions of the TMP1942’s input/output pins.
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
8
1
1
Input/output
Input/output
Input/output
Input/output
Output
Input/output
Output
Output
Output
Output
Output
Output
Input/output
Output
Input/output
Input
Input/output
Input
Input/output
Output
Input/output
Output
Input/output
Input
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Input
Input
Input
Input/output
Input
Output
Input/output
Output
Input
Type
Table 2.2.1 Pin Names and Functions
Port 0: Individually programmable as input or output
Address (Lower): Bits 0-7 of the address/data bus
Port 1: Individually programmable as input or output
Address/Data (Upper): Bits 8-15 of the address/data bus
Address: Bits 8-15 of the address bus
Port 2: Individually programmable as input or output
Address: Bits 0-7 of the address bus
Address: Bits 16-23 of the address bus
Port 30: Output-only
Read Strobe: Asserted during a read operation from an external memory device
Port 31: Output-only
Write Strobe: Asserted during a write operation on D0-D7
Port 32: Programmable as input or output (with internal pull-up resister)
Higher Write Strobe: Asserted during a write operation on D8-D15
Port 33: Programmable as input or output (with internal pull-up resister)
Wait: Causes the CPU to suspend external bus activity
Port 34: Programmable as input or output (with internal pull-up resister)
Bus Request: Asserted by an external bus master to request bus mastership
Port 35: Programmable as input or output (with internal pull-up resister)
Bus Acknowledge: Indicates that the CPU has relinquished the bus in response to
Port 36: Programmable as input or output (with internal pull-up resister)
Read/Write: Indicates the direction of data transfer on the bus: 1 = read or dummy
Port 37: Programmable as input or output (with internal pull-up resister)
This pin is used to select the operating mode during reset. The TMP1940CYAF enters
NORMAL mode when this pin is sampled high at the rising edge of RESET . This pin
should not be pulled down to a logic 0 during a reset sequence. The TMP1940FDBF,
which has an on-chip flash, uses this pin as an interface to the DSU tool. For details,
refer to Part 4, TMP1940FDBF.
Port 40: Programmable as input or output (with internal pull-up resister)
Chip Select 0: Asserted low to enable external devices at programmed addresses
Port 41: Programmable as input or output (with internal pull-up resister)
Chip Select 1: Asserted low to enable external devices at programmed addresses
Port 42: Programmable as input or output (with internal pull-up resister)
Chip Select 2: Asserted low to enable external devices at programmed addresses
Port 43: Programmable as input or output (with internal pull-up resister)
Chip Select 3: Asserted low to enable external devices at programmed addresses
Port 44: Programmable as input or output
System Clock Output: Drives out a clock signal at the same frequency as the CPU
Port 5: Input-only
Analog input: Input to the A/D converter
External start request for the A/D converter (multiplexed with P57)
Port 6: Input-only
Analog input: Input to the A/D converter
Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable)
Port 90: Programmable as input or output
DSU pin
Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable)
TMP1942CY/CZ-9
cycle, 0 = write cycle
BUSRQ
clock (high-speed or low-speed)
.
Function
TX1942CY/CZ