tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 151

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.8.4
3.8.4.1
Functions
This section describes the functions of the DMAC.
Outline
system incorporating the TX19 processor core without the need for any intervention by the TX19
processor core itself.
(1) Source and destination
The DMAC is a 32-bit DMA controller capable of performing high-speed data transfers in a
memory device and an I/O device. The device from which data is transferred is referred to as
the source device and the device to which data is transferred is referred to as the destination
device. Both memory devices and I/O devices can be specified as the source and destination
devices. However, the DMAC can only transfer data from a memory device to an I/O device,
from an I/O device to memory, or from memory to memory; it cannot transfer data between two
I/O devices.
the devices are accessed. When the DMAC accesses an I/O device, it asserts the DACKn signal.
Because only one DACKn signal line is available for each channel, the DMAC can only
perform one data transfer involving an I/O device at a time; hence the DMAC cannot transfer
data from one I/O device to another.
occurs, the interrupt controller generates a request to the DMAC. (In this case, no interrupt
request to the TX19 processor core is generated. For details, refer to Section 3.4, “Interrupts”.)
This interrupt request from the interrupt controller is canceled by the DACKn signal. Therefore,
when an I/O device has been set as a transfer device, a request to the DMAC is cancelled for
each transfer performed (i.e., each time the amount of data specified by the TrSiz bits is
transferred). On the other hand, in memory-to-memory transfers, DACKn is asserted only
when the number of bytes to be transferred (as specified by the value of the BCRn register)
falls to 0; hence several data transfers can be performed successively by a single transfer
request.
internal (or external) memory, although a transfer request from the internal I/O to the DMAC is
cancelled for each transfer performed, the DMAC is kept waiting for the next transfer request
unless the number of bytes to be transferred (as specified by the value of the BCRn register)
falls to 0. Consequently, DMA transfer is performed successively until the BCRn register value
is reduced to 0.
The DMAC performs data transfers between one memory device and another or between a
The difference between memory devices and I/O devices resides in the methods by which
An interrupt source can be specified for transfer requests to the DMAC. When an interrupt
For example, when the DMAC is transferring data between the TMP1942’s internal I/O and
TMP1942CY/CZ-150
TMP1942CY/CZ