tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 207

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tmp19a43fzxbg

Manufacturer Part Number
tmp19a43fzxbg
Description
32bit Tx System Risc
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
TB4MOD
(0xFFFF_
F182)
TB5MOD
(0xFFFF_
F192)
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Must always be set to 00.
Must always be set to 00.
7
0
7
0
6
0
6
0
Figure 3.10.11 TMRB Registers
Software
capture
control
0: Software
1: Don’t care
Software
capture
control
0: Software
1: Don’t care
TB4CP0
TB5CP0
capture
TMP1942CY/CZ-206
capture
TMRB4 mode register
TMRB5 mode register
W *
W *
5
1
5
1
Capture timing
00: Disabled
01: TB4IN0 ↑ TB4IN1 ↑
10: TB4IN0 ↑ TB4IN0 ↓
11: TA3OUT ↑ TA3OUT ↓
Capture timing
00: Disabled
01: Setting prohibited
10: Setting prohibited
11: TA3OUT↑TA3OUT↓
TB4CPM1 TB4CPM0
TB5CPM1 TB5CPM0
Clearing up-counter (UC0)
Capture timing
Software capture
Clearing up-counter (UC0)
Capture timing
Software capture
00
01
10
11
00
01
10
11
0
1
0
1
0
1
0
1
4
0
4
0
Clearing of up-counter disabled
Up-counter cleared when it matches TB4RG1
Capture disabled
Latches value into TB4CP0 at rise of TB4IN0.
Latches value into TB4CP1 at rise of TB4IN1.
Latches value into TB4CP0 at rise of TB4IN0.
Latches value into TB4CP1 at fall of TB4IN0.
Latches value into TB4CP0 at rise of TA3OUT.
Latches value into TB4CP1 at fall of TA3OUT.
Latches up-counter value into TB4CP0.
Don’t care
Clearing of up-counter disabled
Up-counter cleared when it matches TB5RG1
Capture disabled
Capture disabled
Capture disabled
Latches value into TB5CP0 at rise of TA3OUT.
Latches value into TB5CP1 at fall of TA3OUT.
Latches up-counter value into TB5CP0.
Don’t care
3
0
3
0
Up-counter
control
0: Clearing
1: Clearing
Up-counter
control
0: Clearing
1: Clearing
TB4CLE
Capture control
TB5CLE
disabled
enabled
disabled
enabled
R/W
R/W
2
0
2
0
TX1942CY/CZ
11: φT16
Source clock selection
00: TB4IN0 pin input
01: φT1
10: φT4
Source clock selection
00: Setting prohibited
01: φT1
10: φT4
11: φT16
TB4CLK1
TB5CLK1
1
0
1
0
TB4CLK0
TB5CLK0
0
0
0
0

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