tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 159

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.8.4.4
Channel operations
channel is activated, it is checked for errors; if no error is found, it is placed in ready state.
and starts a transfer operation.
forcibly terminated or terminated by an error. This status is indicated by the CSRn register.
A channel is activated when the Str bit in the CCRn register for the channel is set to 1. When a
If a transfer request occurs while a channel is in ready state, the DMAC gains control of the bus
Channel operation may terminate normally or abnormally, for example, when operation is
(1) Starting channel operation
(2) Terminating channel operation
Normal termination
Abnormal termination
placed in ready state. If an error is detected, the channel operation terminates abnormally.
When a channel is placed in ready state, the Act bit in the CSRn register for the channel is set to
1.
immediately, upon which the DMAC will gain control of the bus and start a data transfer. If
external transfer requests have been set for the channel, a transfer request will be generated by
assertion of INTDREQn, upon which the DMAC will gain control of the bus and start a data
transfer.
the CSRn register.
of the CSRn register = 1, channel operation will not start and will terminate abnormally.
will always terminate after the DMAC has finished transferring an amount of data equal to the
unit of data transfer (the value set in the TrSiz field of the CCRn register).
• When data transfer has been completed after the value of the BCRn register has fallen to 0
• Termination due to configuration errors
Channel operation may terminate either normally or abnormally. This status is indicated in
If an attempt is made to set the Str bit in the CCRn register to 1 while the NC bit or AbC bit
A channel is activated when the Str bit in the CCRn register for the channel is set to 1.
When a channel is activated, it is checked for a configuration error; if no error is found, it is
If internal transfer requests have been set for the channel, a transfer request will be generated
Channel operation terminates normally in the following case. Note that, in this case, transfer
Data transfers by the DMAC may terminate abnormally in the following cases:
-Both SIO and DIO are set to 1.
-The CCRn Str bit is set to 1 when the NC bit or AbC bit in the CSRn register = 1.
occurs before the DMAC starts data transfer operation, the SARn, DARn and BCRn
register values will remain as set. When operation for a channel terminates abnormally due
to a configuration error, the Conf bit in the CSRn register is set to 1 at the same time that the
AbC bit is set to 1. Causes of configuration errors are shown below.
A configuration error is an error in the DMA transfer settings. Since a configuration error
TMP1942CY/CZ-158
TMP1942CY/CZ