tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 162

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.8.5
3.8.5.1
Operation
DMAC operations are synchronized to the rising edges of SYSCLK.
Dual-address mode
•
•
Memory-to-memory transfer
transferred from external memory (which is 16 bits wide) to external memory (which is also 16
bits wide). Although it is not shown here, data is transferred successively until the value of the
BCRn register falls to 0.
Memory-to-I/O device transfer
unit of data transfer and the device port size are set to 16 bits and 8 bits, respectively.
RD
A [23 : 16]
CS
CS
WR
AD [15 : 0]
Figure 3.8.16 Dual-Address Mode (Memory to I/O Device)
0
1
Figure 3.8.15 shows a timing example for one transfer session when 16-bit data is being
Figure 3.8.16 shows a timing example for memory-to-I/O device transfer for cases where the
Figure 3.8.15 Dual-Address Mode (Memory to Memory)
A [23 : 16]
AD [15 : 0]
CS
CS
RD
WR
1
0
/
WHR
tsys
tsys
TMP1942CY/CZ-161
Addr
Addr
Read
Data
Read
Data
Addr
Addr
Write
Write
Data
TMP1942CY/CZ
Data
Addr
Write
Data