tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 281

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

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Protocol
The master and slave controllers are placed in 9-bit UART mode.
Each slave controller is enabled for reception by setting SC0MOD0<WU> to 1.
The master controller transmits one frame of data including the 8-bit slave controller selection
code. At this point the most significant bit (bit 8: TB8) is set to 1.
Each slave controller receives the above frame. The slave controller whose selection code
matches the transmitted selection code clears its WU bit to 0.
The master controller transmits data to the selected slave controller (the one whose
SC0MOD0<WU> bit has been cleared to 0). At this point the most significant bit (bit 8: TB8)
is set to 0.
No interrupt (INTRX0) is generated for the slave controllers whose WU bit remains 1 because
the most significant bit of the received data (bit 8: RB8) = 0. These slave controllers ignore the
received data. The slave controller whose WU bit has been cleared to 0 can transmit data to the
master controller so as to notify the master controller that it has finished receiving.
Example settings: Serial link with two slave controllers using the internal clock f
TXD
Master
start
start
RXD
bit 0
bit 0
TMPR1942CY/CZ-280
1
1
as the transfer clock
Slave controller selection code
2
2
TXD
Selection code
3
00000001
3
Slave 1
Data
4
RXD
4
5
5
6
6
TXD
Selection code
00001010
Slave 2
7
7
TMP1942 CY/CZ
RXD
bit 8
“0”
“1”
8
stop
stop
sys/2