tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 327

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Channel-fixed
single conversion
Channel-fixed
repeated
conversion
Channel scan
single conversion
Channel scan
repeated
conversion
Table 3.13.1 Relationship Among A/D Conversion Modes, Interrupt Generation Timing and Flag Operation
Conversion
Channel Converted
Channel Converted
(Note*1) EOCF is cleared when it is read.
(Note*2) If repeat intervals are used with RI set to 1, ADBF indicates 0 during interval periods.
Mode
Note: If the start condition for highest-priority A/D conversion is satisfied during an interval period, highest-priority A/D
conversion is started immediately. Since the interval counter continues running during highest-priority A/D
conversion, the next scan will start when both of the following conditions are satisfied: an overflow of the
interval counter and the completion of highest-priority A/D conversion.
(5) Highest-priority conversion mode
After conversion has been
completed
Every time one conversion
has been completed
Every time four conversions
have been completed
Every time eight conversions
have been completed
After scan conversion has
been completed
Every time one scan
conversion has been
completed
Interrupt Generation
and the next scan conversion being started (repeat interval). This bit is only effective when REPEAT
= 1.
Highest-priority A/D conversion can be started either programmatically by setting
ADMOD2<HPADCE> to 1 or by using a hardware resource as specified with ADMOD4<7:6>. If
highest-priority A/D conversion is started during normal A/D conversion, the converter first stores
the result of the current conversion to the appropriate result register pair, and then performs a single
conversion for the channel specified with ADMOD2<3:0>. The result of that conversion is stored in
ADREGSP, at which point a highest-priority A/D conversion interrupt is generated. Then, normal
A/D conversion is resumed following the last conversion for which the result was stored. Any
condition that triggers highest-priority A/D conversion is ignored while highest-priority A/D
conversion is in progress.
HPADCE is set to 1 during conversion for AN3, the converter will wait for the conversion for AN3
ADMOD0<RI> can be used to control the time between one scan conversion being completed
Repeated scan conversions when RI = 0
Repeated scan conversions when RI = 1
Highest-priority A/D conversion can be performed by interrupting normal A/D conversion.
For example, suppose channel scan repeated conversion is being performed for AN0 to AN8. If
Timing
Example:
0
0
First Scan
First Scan
When repeated scan for channels AN0 to AN2 is set
1
After conversion has been
completed
Every time one conversion
has been completed
Every time four conversions
have been completed
Every time eight conversions
have been completed
After scan conversion has
been completed
Every time one scan
conversion has been
completed
1
EOCF Setting Timing
TMP1942CY/CZ-326
(*1)
2
2
Interval of 8 ADC
clock cycles
ADBF (After Interrupt
0
0
is Generated)
1 (*2)
1 (*2)
1 (*2)
1 (*2)
Second Scan
0
0
1
1
TMP1942CY/CZ
ITM1:0 REPEAT SCAN
Second Scan
00
01
10
⎯
⎯
⎯
2
2
ADMOD0
0
1
0
1
Third Scan
0
0
0
0
1
1