tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 292

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SCL Line
Internal SDA Output
(Master A)
Internal SDA Output
(Master B)
SDA Line
(8) Requesting interrupt service and canceling requests
(9) Serial bus interface operating mode
(10) Monitoring detection of arbitration lost
SCL line is held Low while SBI0CR2<PIN> = 0.
1 when data is written to or read from SBI0DBR. There is a delay of tLOW between PIN being set to
1 and the SCL line being released.
address received matches the value set in I2C0AR or when a general call is received (i.e. when the
eight data bits after the start condition are all 0). Writing a 1 to SBI0CR2<PIN> in the program sets it
to 1; however, writing a 0 to PIN does not clear it to 0.
To use the serial bus interface in I
bus is free before switching from this mode to port mode.
the bus simultaneously), a procedure for arbitrating among masters contending for bus control is
needed in order to guarantee the integrity of data being transferred.
is not output on the SCL or SDA line. The data on the SDA line is used for bus arbitration in I
mode.
on the bus simultaneously. Masters A and B output the same data until the bit at point “a”, at which
point master A outputs a Low signal and master B a High signal. Since the SDA line of the bus has
wired-AND configuration, it is pulled Low by master A. When the SCL line goes High at point “b”,
the slave device latches the SDA line data (i.e. the data output by master A). The data output by
master B at this time has no effect and is ignored. This condition of master B is referred to as
“arbitration lost”. Master B releases the SDA pin so that it will not affect data output by other masters.
If more than one master transmits the same first data word, the arbitration procedure will be
continued on the next and subsequent words.
When a serial bus interface interrupt request (INTS2) occurs, SBI0CR2<PIN> is reset to 0. The
PIN is reset to 0 when the device has finished transmitting or receiving one word of data, and set to
In address recognition mode (i.e. when I2C0CR<ALS> = 0), PIN is reset to 0 when the slave
The SBI0CR2<SBIM1:SBIM0> bits are used to set the operating mode of the serial bus interface.
Since multi-master operation is possible in I
Any attempt to generate a start condition in the bus busy state will result in “arbitration lost”; data
The arbitration procedure is described below using an example in which two masters are residing
Figure 3.12.10 Arbitration Lost
TMP1942CY/CZ-291
2
C bus mode, set SBI0CR2<SBIM1:SBIM0> to 10. Ensure that the
a
b
2
C bus mode (i.e. two or more masters may exist on
Arbitration is lost and the internal
SDA output is driven High
TMP1942CY/CZ
2
C bus