tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 290

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(4) Setting the slave address and selecting address recognition mode
(5) Specifying a master or slave
Internal SCL output (master
A)
Internal SCL output
(master B)
SCL line
Setting ALS to 0 selects address recognition mode.
arbitration lost is detected on the bus, SBI0CR2<MST> is automatically cleared to 0 by hardware.
2)
To operate the device as a slave device, set the slave address in I2C0AR<SA6:SA0> and <ALS>.
Setting SBI0CR2<MST> to 1 causes the device to operate as a master device.
Setting SBI0CR2<MST> to 0 causes the device to operate as a slave device. If a stop condition or
Clock synchronization
of other master devices which are outputting a High clock pulse, thus implementing
wired-AND bus configuration. Therefore, any master which is outputting a High clock pulse
must detect the situation and take appropriate action.
performed correctly even when multiple master devices are present on the bus.
two masters on the bus.
Master B detects this and resets its High-level period count before pulling its internal SCL
output Low.
back High. However, since master B is still holding the SCL line Low, master A does not start
High-level period counting. At point “c”, when master B has released its internal SCL output
back High and the bus SCL line goes High, master A detects these conditions and starts
High-level period counting.
the shortest High-level period and the master connected to the bus which has the longest
Low-level period.
In I
Since the serial bus interface has a clock synchronization function, transfers are always
The clock synchronization procedure is described below using an example in which there are
Master A pulls the internal SCL output Low at point 'a' so that the bus SCL line goes Low.
Master A finishes Low-level period counting at point 'b', releasing its internal SCL output
Thus, the bus clock frequency is determined by the master connected to the bus which has
2
C bus mode, a master device which first pulls the clock line Low will disable the clocks
Figure 3.12.7 Clock Synchronization Example
TMP1942CY/CZ-289
a
Reset High-level
period count
Wait for High-level
period counting
b
c
Start High-level period counting
TMP1942CY/CZ