tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 63

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

INTCLR
(0xFFFF_E060) Read/Write
Note1: Do not clear an interrupt request before reading the corresponding IVR value.
Note2: Follow the steps below to disable a particular interrupt with the Interrupt Controller (INTC).
1. Globally disable the acceptance of interrupts by the core processor by clearing the IEc bit of the
2. Disable the desired interrupt with the INTC by clearing the ILx[2:0] field of the IMCxx register.
3. Execute the SYNC instruction.
4. Enable the acceptance of interrupts by the core processor by setting the IEc bit of the Status
Example:
Status register.
register.
mtc0
sb
sync
mtc0
is to be cleared.
Bit Symbol
After reset
Function
Interrupt request clear register: Sets the value of IVR<LIVR9:LIVR4> for the interrupt whose request
r0, r31
r0, IMC**
$sp, r31
⎯
⎯
⎯
7
; _DI () ;
; IMC** = 0 ;
; _SYNC () ;
; _EI () ;
⎯
⎯
⎯
6
TMP1942CY/CZ-62
Sets the value of IVR<9:4> for the interrupt whose request is to be cleared.
EICLR5
⎯
5
EICLR4
⎯
4
EICLR3
⎯
3
W
TMP1942CY/CZ
EICLR2
⎯
2
EICLR1
⎯
1
EICLR0
⎯
0