tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 141

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.8.2
Request release of bus control
Indicate bus control granted
3.8.2.1
TX19 processor core
Indicate bus control
Configuration
Note * : internal signal
Note : DMA channel priority exists only among those using the same type of bus request
relinquished
Bus control request
Figure 3.8.1 shows how the DMAC is connected internally within the TMP1942.
Internal connections in the TMP1942
(INTDREQn) from the interrupt controller and return an acknowledge signal (
to INTDREQn. The letter ‘n’ denotes the channel number: 0 to 3. Channel 0 has priority over
channel 1, channel 1 has priority over channel 2 and channel 2 has priority over channel 3.
core releasing the core data bus to the DMAC so that the DMAC can access the internal ROM or
internal RAM connected to the TX19 processor core. The DMAC can choose whether or not to use
the snoop function. For details of the snoop function, refer to Section 3.8.2.3, “Snoop function”.
depends on whether or not the DMAC is using the snoop function. GREQ is used to request control
of the bus when the snoop function is not in use and SREQ is used to request control of the bus when
the snoop function is in use. An SREQ bus request has higher priority than a GREQ bus request.
The DMAC has four DMA channels. These channels each receive a data transfer request signal
The TX19 processor core has a snoop function. The snoop function entails the TX19 processor
There are two types of request for bus control: SREQ and GREQ. The type which is selected
signal(SREQ or GREQ).For example, once a given DMA channel has acquired bus
mastership using SREQ, no other DMA channel can assume bus mastership using GREQ
until the ongoing DMA transaction is completed.
Figure 3.8.1 Internal Connection of DMAC Within the TMP1942
Address
Control
Data
INTDREQ [3 : 0]*
TMP1942CY/CZ-140
DMAC
DACK [3 : 0]*
BUSGNT
controller
Interrupt
*
TMP1942CY/CZ
External interrupt
request
Internal I/O interrupt
request
DACKn
BUSREQ
BUSREL
HAVEIT
) in response
*
*
*