tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 289

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.12.5
Control in I
(1) Specifying acknowledgment mode
(2) Selecting the number of bits to be transferred
(3) Serial clock
When operating as the master device, the device allows one extra clock cycle for an acknowledge
signal. In transmitter mode, the device releases the SDA pin during this clock cycle so that it can
receive an acknowledge signal from the receiver. In receiver mode, the device pulls the SDA pin
Low during this clock cycle, thus generating an acknowledge signal.
mode, in which case the device will not generate an extra clock cycle for an acknowledge signal.
transmitted or received.
are always transferred as eight bits. In all other cases, the BC2:BC0 bits hold the value which has
been set.
1)
Setting SBI0CR1<ACK> to 1 causes the serial bus interface to operate in acknowledgment mode.
Setting SBI0CR1<ACK> to 0 causes the serial bus interface to operate in non-acknowledgment
SBI0CR1<BC2:BC0> can be used to specify the number of bits in the next data item to be
Since the BC2:BC0 bits are cleared to 000 as a start condition, the slave address and direction bit
Clock source
serial clock which is output on the SCL pin in master mode.
The SBI0CR1<SCK2:SCK0> bits are used to select the maximum transfer frequency of the
2
C Bus Mode
t
t
fscl = 1/(t
LOW
HIGH
=
t
HIGH
= 2
2n
= 2
φ
T0
Figure 3.12.6 Clock Source
+
n
Low
n
/φT0
/φT0 + 4/φT0
4
TMP1942CY/CZ-288
+ t
HIGH
t
LOW
)
SBI0CR1 <SCK2:0>
000
001
010
011
100
101
110
1/fscl
TMP1942CY/CZ
10
n
4
5
6
7
8
9