tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 299

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Example: When the slave address is matched and the direction bit is 1 in slave receiver mode
INTS2 interrupt
2)
if TRX = 0
Then go to other processing
if AL = 1
Then go to other processing
if AAS = 0
Then go to other processing
SBI0CR1 ← X X X 1 0 X X X
SBI0DBR ← X X X X 0 X X X
Note: X: Don't care
In slave mode (SBI0SR<MST> = 0)
sent by the master is received, or when the data transfer is completed after a general call is
received or the received slave address is found to match the device's address. Also, if the
arbitration-lost condition is detected in master mode, the device will operate in slave mode, in
which case an INTS2 interrupt request will be generated when the device has finished
transferring the word in which the arbitration-lost condition was detected. When an INTS2
interrupt request occurs, SBI0CR2<PIN> is set to 0 and the SCL pin is pulled Low. The SCL
pin is released tLOW after data is written to or read from SBI0DBR, or tLOW after
SBI0CR2<PIN> is set to 1.
or any processing which needs to be performed after the device has entered slave mode upon
detecting the arbitration-lost condition.
Table 3.12.1 shows the various slave mode statuses and the necessary processing for each.
In slave mode, an INTS2 interrupt request is generated when a slave address or general call
In slave mode, perform the processing which normally needs to be performed in slave mode
In each case, test SBI0SR<AL, TRX, AAS, AD0> to determine the necessary processing.
TMP1942CY/CZ-298
Set number of bits to be transmitted.
Set transmit data.
TMP1942CY/CZ