tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 14

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Port C becomes a 5 V port when a 5 V power supply is connected to DVCC52.
Port F becomes a 5 V port when a 5 V power supply is connected to DVCC51.
PF1
RXD5
KEYD
PF2
SCLK5
CTS5
PF3
SCK
PF4
SO
SDA
PF5
SI
SCL
PF6
INT0
ALE
TEST0
TEST1
RSTPUP
DAOUT0-2
NMI
BW0~1
PLLOFF
RESET
VREFH
VREFL
AVCC
AVSS
DAVCC
DAVSS
DAREFH
X1/X2
CVCC
CVSS
DVCC3
DVCC51
DVCC52
DVSS
Pin Name # of Pins
Note: When the DSU is enabled, port 9 functions as the processor probe interfacing signal
regardless of the setting of the port 9 control register (P9CR).
1
1
2
1
1
1
1
1
1
1
2
1
1
4
1
1
5
1
1
1
1
1
1
1
1
3
1
1
Input/output
Input
Input
Input/output
Input/output
Input
Input/output
Input/output
Input/output
Output
Input/output
Input/output
Input
Input/output
Input/output
Input
Output
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input/output
Type
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Port F1: Programmable as input or output
Serial Receive Data 5
Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable)
Port F2: Programmable as input or output
Serial Clock Input/Output 5
Serial Clear-to-Send 5
Programmable as an open-drain output
Port F3: Programmable as input or output
Clock input/output pin when the serial bus interface is in SIO mode
Port F4: Programmable as input or output
Data transmission pin when the serial bus interface is in SIO mode
Data transmission/reception pin when the serial bus interface is in I
Programmable as an open-drain output
Port F5: Programmable as input or output
Data reception pin when the serial bus interface is in SIO mode
Clock input/output pin when the serial bus interface is in I
Programmable as an open-drain output
Port F6: Programmable as input or output
Interrupt request 0: Individually programmable to be high-level, low-level, rising-edge or
Address Latch Enable
(This signal is driven out only when external memory is accessed)
Test pin
Test pin
When this pin is driven high (upon reset), pull-up for ports 3 and 4 is enabled. When this
pin is driven low, pull-up is disabled.
D/A converter output
Non-maskable Interrupt Request: Causes an NMI interrupt on the falling edge
Set both AM0 and AM1 to 1.
This pin should be tied to logic 1 when the frequency multiplied clock from the PLL is
used; otherwise, it should be tied to logic 0.
Reset (with internal pull-up resister): Initializes the whole TMP1940CYAF
Input pin for high reference voltage for the A/D converter.
Input pin for low reference voltage for the A/D converter.
Power supply pin for the A/D converter. This pin should always be connected to power
supply even when the A/D converter is not used.
Ground pin for the A/D converter. This pin should always be connected to ground even
when the A/D converter is not used.
Power supply pin for the D/A converter. This pin should always be connected to power
supply even when the D/A converter is not used.
Ground pin for the D/A converter. This pin should always be connected to ground even
when the D/A converter is not used.
Reference voltage input pin for the D/A converter
Resonator connecting pin
Power supply pin for the oscillator
Ground pin for the oscillator (0 V)
Power supply pins
Power supply pin (port F)
Power supply pin (port C)
Ground pins (0 V)
TMP1942CY/CZ-13
falling-edge sensitive.
Function
TX1942CY/CZ
2
C mode
2
C mode