tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 392

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

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Test-Logic-Reset
When the TAP controller is in the Reset state, the Device Identification register is selected as
default. The three most significant bits of the Boundary-scan register are cleared to 0, disabling
the outputs.
The controller remains in this state while TMS is high. If TMS is held low while the controller is
in this state, then the controller moves to the Run-Test/Idle state.
Run-Test/Idle
In the Run-Test/Idle state, the IC is put in a test mode only when certain instructions such as a
built-in self test (BIST) instruction are present. For instructions that do not cause any activities
in this state, all test data registers selected by the current instruction retain their previous states.
The controller remains in this state while TMS is held low. When TMS is high, the controller
moves to the Select-DR-Scan state.
Select-DR-Scan
This is a temporary controller state. Here, the IC does not execute any specific functions.
If TMS is held low when the controller is in this state, then the controller moves to the
Capture-DR state. If TMS is held high, the controller moves to the Select-IR-Scan state in the
instruction column.
Select-IR-Scan
This is a temporary controller state. Here, the IC does not execute any specific functions.
If TMS is held low when the controller is in this state, then the controller moves to the
Capture-IR state. If TMS is held high, the controller returns to the Test-Logic-Reset state.
Capture-DR
In this controller state, if the test data register selected by the current instruction on the rising
edge of TCK has parallel inputs, then data can be parallel-loaded into the shift portion of the
data register. If the test data register does not have parallel inputs, or if data need not be loaded
into the selected data register, then the data register retains its previous state.
If TMS is held low while the controller is in this state, the controller moves to the Shift-DR state.
If TMS is held high, the controller moves to the Exit1-DR state.
Shift-DR
In this controller state, the test data register connected between TDI and TDO shifts data one
stage forward towards its serial output.
When the controller is in this state, then it remains in the Shift-DR state if TMS is held low, or
moves to the Exit1-DR state if TMS is held high.
TMP1942CY/CZ-391
TMP1942CY/CZ