r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 1126

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Clock Pulse Generator
23.3
The system-clock PLL circuit and divider have the function of multiplying the frequency of the
clock from the oscillator by a factor of 1, 2, or dividing by 2. The system clock frequency is set
with the STC1 and STC0 bits in PLLCR. The phase of the rising edge of the internal clock is
controlled so as to match that of the rising edge of the EXTAL pin.
When the frequency is changed with the system-clock PLL circuit and divider, operation varies
according to the setting of the STCS bit in SCKCR.
When STCS = 0, the setting of the changed frequency becomes valid after a transition to software
standby mode. The transition time count is performed in accordance with the setting of bits STS3
to STS0 in SBYCR. For details on SBYCR, see section 24.1.1, Standby Control Register
(SBYCR).
1. The initial PLL circuit multiplication factor is 1.
2. A value is set in bits STS3 to STS0 to give the specified transition time.
3. The target value is set in bits STC1 and STC0, and a transition is made to software standby
4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.
5. Software standby mode is cleared, and a transition time is secured in accordance with the
6. After the set transition time has elapsed, this LSI resumes operation using the target
When STCS = 1, a change to the frequency setting becomes effective a maximum of four cycles
after the setting is changed. If the clock frequency is changed during access to an external address
space, correct operation cannot be guaranteed. Therefore, be sure to store instructions that change
the STC1 and STC0 bits and other instructions to be executed within a maximum of four cycles
after the change to the frequency setting in on-chip ROM or on-chip RAM, so that instructions do
not access an external address space before the frequency clock is switched over.
Rev. 1.00 Sep. 19, 2008 Page 1098 of 1270
REJ09B0466-0100
mode.
setting in STS3 to STS0.
multiplication factor.
System-Clock PLL Circuit and Divider