r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 282

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 Bus Controller (BSC)
6.8.10
By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is
inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled.
Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to
synchronous DRAM read access. Figure 6.60 shows the write access timing when the CAS
latency control cycle is disabled.
Rev. 1.00 Sep. 19, 2008 Page 254 of 1270
REJ09B0466-0100
Figure 6.60 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled
DQMU, DQML
Precharge-sel
Address bus
Bus Cycle Control in Write Cycle
SDRAMφ
Data bus
CKE
RAS
CAS
WE
φ
Column address
PALL
T
p
Row address
Row address
(SDWCD = 1)
ACTV
T
r
High
NOP
T
c1
Column address
T
WRIT
c2