r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 360

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 DMA Controller (DMAC)
Rev. 1.00 Sep. 19, 2008 Page 332 of 1270
REJ09B0466-0100
Bit
4
3
Bit Name
DTE0
DTIE1B
Initial Value
0
0
R/W
R/W
R/W
Description
Data Transfer Enable 0
Enables or disables DMA transfer for the
activation source selected by the DTF3 to DTF0
bits in DMACR of channel 0.
When DTE0 = 0, data transfer is disabled and the
activation source is ignored. If the activation
source is an internal interrupt, an interrupt request
is issued to the CPU or DTC. If the DTE0 bit is
cleared to 0 when DTIE0 = 1, the DMAC regards
this as indicating the end of a transfer, and issues
a transfer end interrupt request to the CPU.
When DTE0 = 1 and DTME0 = 1, data transfer is
enabled and the DMAC waits for a request by the
activation source. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
•
•
•
[Setting condition]
When 1 is written to the DTE0 bit after reading
DTE0 = 0
Data Transfer Interrupt Enable 1B
Enables or disables an interrupt to the CPU or
DTC when transfer on channel 1 is interrupted. If
the DTME1 bit is cleared to 0 when DTIE1B = 1,
the DMAC regards this as indicating a break in the
transfer, and issues a transfer break interrupt
request to the CPU or DTC.
A transfer break interrupt can be canceled either
by clearing the DTIE1B bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the DTME1 bit to 1.
When initialization is performed
When the specified number of transfers have
been completed
When 0 is written to the DTE0 bit to forcibly
suspend the transfer, or for a similar reason