r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 512

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Data Transfer Controller (DTC)
Table 9.7
Legend:
N: Block size (initial setting of CRAH and CRAL)
Table 9.8
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev. 1.00 Sep. 19, 2008 Page 484 of 1270
REJ09B0466-0100
Mode
Normal
Repeat
Block transfer
Object to be Accessed
Bus width
Access states
Execution
status
Number of execution states = I · S
DTC Execution Status
Number of States Required for Each Execution Status
Vector read
Register information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation
Vector Read
I
1
1
1
Register Information
Read/Write
J
6
6
6
S
S
S
S
S
S
S
I
J
K
K
L
L
M
On-
Chip
RAM
32
—
1
1
1
1
1
1
I
+ Σ (J · S
On-
Chip
ROM
16
—
1
1
1
1
1
1
J
On-Chip I/O
Registers
+ K · S
—
—
8
2
2
4
2
4
Data Read
K
1
1
N
K
+ L · S
16
—
—
2
2
2
2
2
1
External Devices
L
) + M · S
—
2
4
2
4
2
4
Data Write
L
1
1
N
8
6+2m
6+2m
6+2m
3+m
3+m
—
3
M
Internal
Operations
M
3
3
3
—
2
2
2
2
2
2
16
3+m
3+m
3+m
3+m
3+m
—
3