r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 326

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 Bus Controller (BSC)
6.12
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters except the EXDMAC* continue to operate as long
as there is no external access. If any of the following requests are issued in the external bus
released state, the BREQO signal can be driven low to output a bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
Note: * Not supported by the H8S/2424 Group.
6.12.1
In externally expanded mode, the bus can be released to an external device by setting the BRLE
bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus released state.
In the external bus released state, internal bus masters except the EXDMAC can perform accesses
using the internal bus. When an internal bus master wants to make an external access, it
temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus
master to be canceled. If a refresh request is generated in the external bus released state, or if a
SLEEP instruction is executed to place the chip in software standby mode or all-module-clocks-
stopped mode, refresh control and software standby or all-module-clocks-stopped control is
deferred until the bus request from the external bus master is canceled.
If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the
following requests are issued, to request cancellation of the bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
Rev. 1.00 Sep. 19, 2008 Page 298 of 1270
REJ09B0466-0100
module-clocks-stopped mode
module-clocks-stopped mode
Bus Release
Operation