r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 855

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

14.3.3
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by overflows.
Note:
Bit
7
6
5
4 to 0
*
Bit Name
WOVF
RSTE
—
—
Reset Control/Status Register (RSTCSR)
Only a write of 0 is permitted, to clear the flag.
Initial Value
0
0
0
All 1
R/W
R/(W) *
R/W
R/W
—
Description
Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and only 0 can be written.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1,
and then writing 0 to WOVF
Reset Enable
Specifies whether or not a reset signal is
generated in the chip if TCNT overflows during
watchdog timer operation.
0: Reset signal is not generated even if TCNT
1: Reset signal is generated if TCNT overflows
Reserved
Can be read and written, but does not affect
operation.
Reserved
These bits are always read as 1 and cannot be
modified.
overflows
(Though this LSI is not reset, TCNT and TCSR
in WDT are reset)
Rev. 1.00 Sep. 19, 2008 Page 827 of 1270
Section 14 Watchdog Timer (WDT)
REJ09B0466-0100