r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 12

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

6.4
6.5
6.6
6.7
Rev. 1.00 Sep. 19, 2008 Page xii of xxviii
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10 DRAM Access Control Register (DRACCR)....................................................... 175
6.3.11 Refresh Control Register (REFCR) ...................................................................... 178
6.3.12 Refresh Timer Counter (RTCNT)......................................................................... 181
6.3.13 Refresh Time Constant Register (RTCOR) .......................................................... 181
Bus Control........................................................................................................................ 182
6.4.1
6.4.2
6.4.3
6.4.4
Basic Bus Interface ............................................................................................................ 188
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
Address/Data Multiplexed I/O Interface............................................................................ 202
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
6.6.8
DRAM Interface ................................................................................................................ 216
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.7.8
6.7.9
Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 163
Bus Control Register (BCR) ................................................................................. 164
Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 166
DRAM Control Register (DRAMCR) .................................................................. 167
Area Division........................................................................................................ 182
Bus Specifications ................................................................................................ 183
Memory Interfaces................................................................................................ 185
Chip Select Signals ............................................................................................... 187
Data Size and Data Alignment.............................................................................. 188
Valid Strobes ........................................................................................................ 189
Basic Timing......................................................................................................... 190
Wait Control ......................................................................................................... 198
Read Strobe (RD) Timing..................................................................................... 199
Extension of Chip Select (CS) Assertion Period................................................... 201
Setting Address/Data Multiplexed I/O Space ....................................................... 202
Address/Data Multiplexing................................................................................... 202
Data Bus ............................................................................................................... 203
Address Hold Signal ............................................................................................. 203
Basic Timing......................................................................................................... 203
Wait Control ......................................................................................................... 212
Read Strobe (RD) Timing..................................................................................... 213
Extension of Chip Select (CS) Assertion Period in Data Cycle............................ 214
Setting DRAM Space............................................................................................ 216
Address Multiplexing ........................................................................................... 216
Data Bus ............................................................................................................... 217
Pins Used for DRAM Interface............................................................................. 218
Basic Timing......................................................................................................... 219
Column Address Output Cycle Control ................................................................ 221
Row Address Output State Control....................................................................... 222
Precharge State Control ........................................................................................ 224
Wait Control ......................................................................................................... 225