r4f2426 Renesas Electronics Corporation., r4f2426 Datasheet - Page 397

• Manufacturer Part Number: r4f2426
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

(4)
Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to
external 16-bit, 2-state access space.
A one-block transfer is performed for a single transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-
state DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is
generated during data transfer, block transfer operation is not affected until data transfer for one
block has ended.
(5)
Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected.
Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge.
Address bus
Full Address Mode (Block Transfer Mode)
DREQ Pin Falling Edge Activation Timing
TEND
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)
Bus release
HWR
LWR
RD
φ
DMA
read
DMA
write
Block transfer
DMA
read
DMA
write
DMA
dead
Bus release
DMA
read
Rev. 1.00 Sep. 19, 2008 Page 369 of 1270
DMA
write
Last block transfer
Section 7 DMA Controller (DMAC)
DMA
read
DMA
write
REJ09B0466-0100
DMA
dead
Bus
release