s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 112

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

23 Asynchronous Operation
23.1
23.2 Asynchronous Write Operation
23.3 Asynchronous Write Operation in Synchronous Mode
110
Asynchronous 4 Page Read Operation
Asynchronous normal read operation starts when CS#, OE# and UB# or LB# are driven to V
under the valid address without toggling page addresses (A0, A1). If the page addresses (A0, A1)
are toggled under the other valid address, the first data will be out with the normal read cycle
time (t
(MRS# and WE# should be driven to V
ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
Asynchronous write operation starts when CS#, WE# and UB# or LB# are driven to V
valid address. MRS# and OE# should be driven to V
Clock, ADV#, WAIT# signals are ignored during the asynchronous (page) read operation.
A write operation starts when CS#, WE# and UB# or LB# are driven to V
dress. Clock input does not have any affect to the write operation (MRS# and OE# should be
driven to V
Clock, ADV#, and WAIT# signals are ignored during the asynchronous (page) read operation.
RC
) and the second, the third and the fourth data will be out with the page cycle time (t
IH
during write operation. ADV# can be either toggling for address latch or held in V
UB#, LB#
Data Out
UB#, LB#
A22~A2
Address
Data out
Data in
A1 ~A0
OE#
WE#
CS#
CS#
Figure 23.1 Asynchronous 4-Page Read
A d v a n c e
S71WS-Nx0 Based MCPs
Figure 23.2 Asynchronous Write
IH
High-Z
High-Z
during the asynchronous (page) read operation) Clock,
I n f o r m a t i o n
IH
during the asynchronous write operation.
High- Z
S71WS-N_01_A4 September 15, 2005
IL
under the valid ad-
IL
under the
PC
IL
IL
).
).