s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 22

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

General Description
Distinctive Characteristics
Performance Characteristics
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not
design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
S29WS-N MirrorBit
S29WS256N, S29WS128N
256/128 Megabit (16/8 M x 16 bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst-mode Flash Memory
Max. Synch. Latency, ns (t
Max. Synch. Burst Access, ns (t
Max. Asynch. Access Time, ns (t
Max CE# Access Time, ns (t
Max OE# Access Time, ns (t
The Spansion S29WS256/128 are Mirrorbit
These burst mode Flash devices are capable of performing simultaneous read and write operations with
zero latency on two separate banks using separate data and address pins. These products can operate up
to 80 MHz and use a single V
applications requiring higher density, better performance and lowered power consumption.
Single 1.8 V read/program/erase (1.70–1.95 V)
110 nm MirrorBit™ Technology
Simultaneous Read/Write operation with zero
latency
32-word Write Buffer
Sixteen-bank architecture consisting of 16/8
Mwords for WS256N/128N, respectively
Four 16 Kword sectors at both top and bottom of
memory array
254/126 64 Kword sectors (WS256N/128N)
Programmable linear (8/16/32) with or without
wrap around and continuous burst read modes
Secured Silicon Sector region consisting of 128
words each for factory and customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector
(typical)
RDY output indicates data available to system
Speed Option (MHz)
Publication Number S71WS-N_01
Read Access Times
IACC
CE
OE
)
)
)
BACC
ACC
)
)
CC
13.5
of 1.7 V to 1.95 V that makes them ideal for today’s demanding wireless
80
80
80
80
9
TM
11.2
13.5
66
80
80
80
Flash Family
Revision A
TM
13.5
13.5
54
80
80
80
Flash products fabricated on 110-nm process technology.
Amendment 4
Continuous Burst Read @ 80 MHz
Simultaneous Operation (asynchronous)
Program (asynchronous)
Erase (asynchronous)
Standby Mode (asynchronous)
Single Word Programming
Effective Write Buffer Programming (V
Effective Write Buffer Programming (V
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
Command set compatible with JEDEC (42.4)
standard
Hardware (WP#) protection of top and bottom
sectors
Dual boot sector configuration (top and bottom)
Low V
Persistent and Password methods of Advanced
Sector Protection
Write operation status bits indicate program and
erase operation completion
Suspend and Resume commands for Program and
Erase operations
Unlock Bypass program command to reduce
programming time
Synchronous or Asynchronous program operation,
independent of burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
CC
write inhibit
Current Consumption (typical values)
Issue Date September 15, 2005
Typical Program & Erase Times
ACC
CC
) Per Word
INFORMATION
) Per Word
ADVANCE
150 ms
600 ms
38 mA
50 mA
19 mA
19 mA
9.4 µs
20 µA
40 µs
6 µs