s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 44

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

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10.5.4
10.5.5
Cycle
1
2
3
4
5
6
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all
zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip
contain FFFFh. The system is not required to provide any controls or timings during these oper-
ations. The “Command Definition” section in the appendix shows the address and data
requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. Refer to “Write Operation Status” for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
The following is a C source code example of using the chip erase function. Refer to the Span-
sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for
general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
Erase Suspend/Erase Resume Commands
When the Erase Suspend command is written during the sector erase time-out, the device imme-
diately terminates the time-out period and suspends the erase operation. The Erase Suspend
command allows the system to interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. The bank address is required when writing
this command. This command is valid only during the sector erase operation, including the min-
imum t
command is ignored if written during the chip erase operation.
When the Erase Suspend command is written after the t
ing the sector erase operation, the device requires a maximum of t
suspend the erase operation. Additionaly, when an Erase Suspend command is written during an
active erase operation, status information is unavailable during the transition from the sector
erase operation to the erase suspended state.
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
Chip Erase Command
Setup Command
SEA
Description
Unlock
Unlock
Unlock
Unlock
time-out period during the sector erase command sequence. The Erase Suspend
Table 10.16 Software Functions and Sample Code
A d v a n c e
*/
S71WS-Nx0 Based MCPs
Operation
Write
Write
Write
Write
Write
Write
Base + AAAh
Base + 554h
Base + AAAh
Base + AAAh
Base + 554h
Base + AAAh
Byte Address
/* write unlock cycle 1
/* write unlock cycle 2
/* write setup command
/* write additional unlock cycle 1 */
/* write additional unlock cycle 2 */
/* write chip erase command
I n f o r m a t i o n
Table
SEA
Word Address
Base + 555h
Base + 2AAh
Base + 555h
Base + 555h
Base + 2AAh
Base + 555h
time-out period has expired and dur-
15.1. These commands invoke the
ESL
(erase suspend latency) to
S71WS-N_01_A4 September 15, 2005
*/
*/
*/
*/
00AAh
00AAh
0055h
0080h
0055h
0010h
Data