s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 115

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

25.4 Burst Stop
25.5 Wait Control (WAIT#)
September 15, 2005 S71WS-N_01_A4
Data out
Data in
CLK
ADV#
CS#
Read
Write
Burst stop is used when the system wants to stop burst operation on purpose. If driving CS# to
V
operation, the new burst operation cannot be issued. The new burst operation can be issued only
after the previous burst operation is finished.
The burst stop feature is very useful because it enables the user to utilize the unsupported burst
length such as 1 burst or 2 burst, used mostly in the mobile handset application environment.
The WAIT# signal indicates to the host system when it’s data-out or data-in is valid.
To be compatible with the Flash interfaces of various microprocessor types, the WAIT# polarity
(WP) can be configured. The polarity can be programmed to be either low enable or high enable.
For the timing of the WAIT# signal, it should be set active one clock prior to the data regardless
of Read or Write cycle.
Note:
WAIT#
WAIT#
IH
during the burst read operation, then the burst operation is stopped. During the burst read
LATENCY: 5, Burst Length: 4, WP: Low Enable
High -Z
High -Z
A d v a n c e
0
1
Figure 25.2 WAIT# and Read/Write Latency Control
Latency 5
Latency 5
2
I n f o r m a t i o n
S71WS-Nx0 Based MCPs
3
D0
4
D1
5
DQ0
D2
6
DQ1
D3
7
DQ2
8
DQ3
9
10
11
12
13
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