s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 30

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

28
In all cases, with or without latency, the RDY output indicates when the next data is available to
be read.
Tables 10.2-10.7
uration Register” table (CR11 - CR14) and timing diagrams for more details.
Word
Word
Word
Table 10.5 Address/Boundary Crossing Latency (S29WS256N @ 66 MHz)
Word
Table 10.4 Address/Boundary Crossing Latency (S29WS256N @ 80MHz)
starting address: whether the address is divisible by four (where A[1:0] is 00). A divisible-
by-four address incurs the least number of additional wait states that occur after the initial
word. The number of additional wait states required increases for burst operations in which
the starting address is one, two, or three locations above the divisible-by-four address (i.e.,
where A[1:0] is 01, 10, or 11).
boundary crossing: There is a boundary at every 128 words due to the internal architecture
of the device. One additional wait state must be inserted when crossing this boundary if the
memory bus is operating at a high clock frequency. Please refer to the tables below.
clock frequency: the speed at which the device is expected to burst data. Higher speeds
require additional wait states after the initial word for proper operation.
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
Wait States
Wait States
Wait States
Wait States
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
5, 6, 7 ws
7 ws
7 ws
7 ws
7 ws
6 ws
6 ws
6 ws
x ws
x ws
x ws
x ws
6 ws
reflect wait states required for S29WS256/128N devices. Refer to the “Config-
Table 10.2 Address Latency (S29WS256N)
Table 10.3 Address Latency (S29WS128N)
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
1 ws
1 ws
A d v a n c e
1 ws
1 ws
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
S71WS-Nx0 Based MCPs
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D2
D3
D2
D3
D2
D3
D2
D3
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D3
D3
D3
D3
I n f o r m a t i o n
Cycle
Cycle
Cycle
Cycle
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D4
D4
D4
D4
D4
D4
D4
D4
1 ws
1 ws
1 ws
1 ws
D5
D5
D5
D5
D5
D5
D5
D5
D4
D4
D4
D4
D6
D6
D6
D6
D6
D6
D6
D6
D4
D4
D4
D4
D5
D5
D5
D5
D7
D7
D7
D7
D7
D7
D7
D7
D5
D5
D5
D5
D6
D6
D6
D6
S71WS-N_01_A4 September 15, 2005
D8
D8
D8
D8
D8
D8
D8
D8
D6
D6
D6
D6
D7
D7
D7
D7