s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 137

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

September 15, 2005 S71WS-N_01_A4
Latency = 5, Burst Length = 4, WP = Low enable (OE# = V
CS# Low Holding Consecutive Burst Write
Notes:
1.
2.
3.
4.
5.
6.
LB#, UB#
WAIT#
CLK
ADV
Address
CS#
WE#
Data in
The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
D2 is masked by UB# and LB#.
The consecutive multiple burst read operation with holding CS# low is possible only through issuing a new ADV# and
address.
Burst Cycle Time (t
BEADV
Symbol
t
t
t
t
t
t
BMS
BMH
WES
WEH
BS
BH
should be met.
A d v a n c e
WL
WH
High-Z
t
WZ
AS(B)
or t
): Data available (driven by Latency-1 clock)
t
): Data don’t care (driven by CS# high going edge)
t
WES
BC
CSS(B)
AWL
Valid
Valid
Min
Figure 32.7 Timing Waveform of Burst Write Cycle (2)
) should not be over 2.5µs.
0
5
5
7
7
5
5
t
WL
): Data not available (driven by CS# low going edge or ADV# low going edge)
T
t
ADVS
Speed
t
ADVH
Table 32.6 Burst Write AC Characteristics
1
t
t
AH(B)
WEH
I n f o r m a t i o n
Latency 5
Max
S71WS-Nx0 Based MCPs
—
—
—
—
—
—
2
t
WH
Don’t Ca re
3
t
BC
t
t
Units
BS
DS
ns
D0
4
t
DHC
t
BH
D1
5
t
BMS
D2
6
Symbol
t
t
t
t
t
t
WHP
DHC
AWL
WH
WL
DS
t
D3
BMH
7
t
DHC
IH
, MRS# = V
t
WHP
t
BEADV
8
Valid
Valid
Min
—
—
—
5
5
3
9
t
AWL
Speed
IH
10
).
Latency 5
Max
10
10
12
—
—
—
11
t
WH
12
Units
D0
ns
13
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