s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 14

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

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Input/Output Descriptions
Table 3.1
A23-A0
DQ15-DQ0
OE#
WE#
V
NC
RDY
CLK
AVD#
F-RST#
F-WP#
F-ACC
R-CE1#
F1-CE#
F2-CE#
R-MRS
F-VCC
R-VCC
R-UB#
R-LB#
DNU
SS
Symbol
identifies the input and output package connections provided on the device.
Address inputs
Data input/output
Output Enable input. Asynchronous relative to CLK for the Burst mode.
Write Enable input.
Ground
No Connect; not connected internally
Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY.
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment
the internal address counter. Should be at V
Address Valid input. Indicates to device that the valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be
latched.
High = device ignores address inputs
Hardware reset input. Low = device resets and returns to reading array data
Hardware write protect input. At V
sectors. Should be at V
Accelerated input. At V
mode. At V
Chip-enable input for pSRAM.
Chip-enable input for Flash 1. Asynchronous relative to CLK for Burst Mode.
Chip-enable input for Flash 2. Asynchronous relative to CLK for Burst Mode. This applies to the 512Mb
MCP only.
Mode register select for Type 4.
Flash 1.8 Volt-only single power supply.
pSRAM Power Supply.
Upper Byte Control (pSRAM).
Lower Byte Control (pSRAM)
Do Not Use
IL
, disables all program and erase functions. Should be at V
A d v a n c e
Table 3.1 Input/Output Descriptions
S71WS-Nx0 Based MCPs
HH
IH
, accelerates programming; automatically places device in unlock bypass
for all other conditions.
IL
, disables program and erase functions in the four outermost
I n f o r m a t i o n
IL
Description
or V
IH
while in asynchronous mode
IH
S71WS-N_01_A4 September 15, 2005
for all other conditions.