s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 28

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

10 Device Operations
10.1
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.
10.2
26
Operation
Asynchronous Read - Addresses Latched
Asynchronous Read - Addresses Steady State
Asynchronous Write
Synchronous Write
Standby (CE#)
Hardware Reset
Burst Read Operations (Synchronous)
Load Starting Burst Address
Advance Burst to next address with appropriate
Data presented on the Data Bus
Terminate current Burst read cycle
Terminate current Burst read cycle via RESET#
Terminate current Burst read cycle and start new
Burst read cycle
Device Operation Table
Asynchronous Read
This section describes the read, program, erase, simultaneous read/write operations, handshak-
ing, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see Tables
does not occupy any addressable memory location; rather, it is composed of latches that store
the commands, along with the address and data information needed to execute the command.
The contents of the register serve as input to the internal state machine and the state machine
outputs dictate the function of the device. Writing incorrect address and data values or writing
them in an improper sequence may place the device in an unknown state, in which case the sys-
tem must write the reset command to return the device to the reading array data mode.
The device must be setup appropriately for each operation.
state of each control pin for any particular operation.
All memories require access time to output array data. In an asynchronous read operation, data
is read from one memory location at a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes the data on its outputs to arrive asyn-
chronously with the address on its inputs.
The device defaults to reading array data asynchronously after device power-up or hardware re-
set. To read data from the memory array, the system must first assert a valid address on A
A0, while driving AVD# and CE# to V
the address. The OE# signal must be driven to V
output on A/DQ15-A/DQ0 pins after the access time (t
OE#.
Table 10.1 Device Operations
CE#
A d v a n c e
H
X
H
X
L
L
L
L
L
L
L
S71WS-Nx0 Based MCPs
OE#
H
H
X
X
X
X
X
X
L
L
L
IL
. WE# must remain at V
WE#
H
H
X
X
H
H
H
H
H
L
L
I n f o r m a t i o n
Addresses
IL
Addr In
Addr In
Addr In
Addr In
Addr In
Addr In
, once AVD# has been driven to V
X
X
X
X
X
15.1
OE
) has elapsed from the falling edge of
and 15.2). The command register itself
Data Out
Data Out
Data Out
HIGH Z
HIGH Z
HIGH Z
HIGH Z
DQ15–0
IH
Table 10.1
Burst
I/O
I/O
I/O
. The rising edge of AVD# latches
X
RESET#
S71WS-N_01_A4 September 15, 2005
describes the required
H
H
H
H
H
H
H
H
H
L
L
CLK
X
X
X
X
X
X
IH
. Data is
AVD#
X
X
H
X
X
L
L
max
–