s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 159

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

42 Low Power Features
42.1
42.2 Driver Strength Optimization
42.3 Partial Array Refresh (PAR) mode
September 15, 2005 S71WS-N_01_A4
Internal TCSR
The internal Temperature Compensated Self Refresh (TCSR) feature is a very useful tool for re-
ducing standby current at room temperature (below 40°C). DRAM cells have weak refresh
characteristics in higher temperatures. High temperatures require more refresh cycles, which can
lead to standby current increase.
Without the internal TCSR, the refresh cycle should be set at worst condition so as to cover the
high temperature (85°C) refresh characteristics. But with internal TCSR, a refresh cycle below
40°C can be optimized, so the standby current at room temperature can be greatly reduced. This
feature is beneficial since most mobile phones are used at or below 40°C in the phone standby
mode.
Notes:
1.
2.
The optimization of output driver strength is possible through the mode register setting to adjust
for the different data loadings. Through this driver strength optimization, the device can minimize
the noise generated on the data bus during read operation. The device supports full drive, 1/2
drive and 1/4 drive.
The PAR mode enables the user to specify the active memory array size. The pSRAM consists of
4 blocks and the user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory arrays
through the Mode Register Setting. The active memory array is periodically refreshed whereas
the disabled array is not refreshed, so the previously stored data is lost. Even though PAR mode
is enabled through the Mode Register Setting, PAR mode execution by the MRS# pin is still
needed. The normal operation can be executed even in refresh-disabled array as long as the
MRS# pin is not driven to the Low condition for over 0.5µs. Driving the MRS# pin to the High
condition puts the device back to the normal operation mode from the PAR executed mode. Refer
to
Partial Refresh(3/4 Block)
Partial Refresh(1/2 Block)
Partial Refresh(1/4 Block)
Figure 42.1
Only the data in the refreshed block are valid.
The PAR Array can be selected through Mode Register Set (see
Standby (Full Array)
Power Mode
A d v a n c e
and
Table 42.1
MODE
000000h
000000h
000000h
000000h
MRS#
CS#
Figure 42.1 PAR Mode Execution and Exit
(Bottom Array)
I n f o r m a t i o n
Table 42.1 PAR Mode Characteristics
Address
(note 2)
S71WS-Nx0 Based MCPs
for PAR operation and PAR address mapping.
Normal
Operation
–
–
–
–
7FFFFFh
5FFFFFh
3FFFFFh
1FFFFFh
Suspend
0.5 µs
000000h
200000h
400000h
600000h
(Top Array)
Address
(note 2)
–
–
–
–
PAR mode
7FFFFFh
7FFFFFh
7FFFFFh
7FFFFFh
Mode Register Setting
Valid (note 1)
Memory Cell
Data
Normal
Operation
Operation).
Standby Current
(µA, Max)
200
170
150
140
Wait Time
(µs)
0
157