s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 168

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

166
47.3.1
Asynchronous Write Timing Waveform in Synchronous Mode
47.3.1.1 Write Cycle (Low ADV# Type)
MRS# = V
Notes:
1.
2.
3.
4.
5.
6.
Notes:
1.
2.
CS#
UB#, LB#
Data out
CLK
ADV#
Address
WE#
Data in
Low ADV# type write cycle - WE# Controlled.
A write occurs during the overlap (tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high or WE# goes high. The t
beginning of write to the end of write.
t
t
t
going high.
Clock input does not have any affect to the write operation if the parameter t
Low ADV# Type, WE# Controlled.
tWP(min) = 70ns for continuous write operation over 50 times.
CW
AS
WR
Symbol
t
t
t
t
t
is measured from the address valid to the beginning of write.
WC
CW
AW
BW
WP
is measured from the CS# going low to the end of write.
is measured from the end of write to the address change. t
Table 47.6 Asynchronous Write in Synchronous Mode AC Characteristics
IH
, OE# = V
t
Figure 47.7 Timing Waveform Of Write Cycle (Low ADV# Type)
0
AS
55 (note 2)
1
IH
Read Latency 5
Min
70
60
60
60
, WAIT# = High-Z, WE# Controlled
High-Z
2
Speed
t
A d v a n c e
WLRL
S71WS-Nx0 Based MCPs
3
t
t
4
CW
AW
t
WC
Max
t
t
BW
—
—
—
—
—
WP
5
I n f o r m a t i o n
Units
6
ns
WR
7
t
is applied in case a write ends with CS# or WE#
DW
Dat a Valid
Symbol
8
t
WLRL
t
t
t
t
WR
DW
DH
AS
WLRL
9
t
DH
t
WR
is met.
10
High- Z
Min
30
1
0
0
0
S71WS-N_01_A4 September 15, 2005
11
Speed
WP
is measured from the
Max
12
—
—
—
—
—
13
clock
Units
ns
14