s71ws256nc0bawa30 Meet Spansion Inc., s71ws256nc0bawa30 Datasheet - Page 95

• Manufacturer Part Number: s71ws256nc0bawa30
• Description: Stacked Multi-chip Product Mcp 256/512/128 Megabit 32m/16m/8m X 16 Bit Cmos 1.8 Volt-only Simultaneous Read/write, Burst-mode Flash Memory With 128/64megabit 8m/4m X 16-bit Psram.
• Manufacturer: Meet Spansion Inc.

September 15, 2005 S71WS-N_01_A4
Legend:
X = Don’t care.
RA = Address of the memory location to be read.
PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must
be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must
be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14.
Notes:
1.
2.
3.
4.
5.
6.
7.
Protection (PPB)
Volatile Sector
Volatile Sector
Non-Volatile
(PPB Lock)
Protection
Protection
Protection
Password
Register
All values are in hexadecimal.
Shaded cells indicate read cycles.
Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
If both the Persistent Protection Mode Locking Bit and the
Password Protection Mode Locking Bit are set at the same time,
the command operation aborts and returns the device to the
default Persistent Sector Protection Mode during 2nd bus cycle.
Note that on all future devices, addresses equal 00h, but is
currently 77h for the WS256N only. See Tables
explanation of lock bits.
Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
Sector
Freeze
Global
(DYB)
Lock
Bits
Command Sequence
Command Set Entry (5)
Program (6, 12)
Read (6)
Command Set Exit (7)
Command Set Entry (5)
Program [0-3] (8)
Read (9)
Unlock
Command Set Exit (7)
Command Set Entry (5)
PPB Program (10)
All PPB Erase (10, 11)
PPB Status Read
Command Set Exit (7)
Command Set Entry (5)
PPB Lock Bit Set
PPB Lock Bit Status Read
Command Set Exit (7)
Command Set Entry (5)
DYB Set
DYB Clear
DYB Status Read
Command Set Exit (7)
(Notes)
A d v a n c e
3
2
1
2
3
2
4
7
2
3
2
2
1
2
3
2
1
2
3
2
2
1
2
Table 15.2 Sector Protection Commands
0...00
Addr
555
555
555
555
555
XX
77
XX
XX
00
XX
XX
XX
SA
XX
XX
BA
XX
XX
XX
SA
XX
First
11.1
PWD0
RD(0)
RD(0)
RD(0)
Data
data
AA
A0
90
AA
A0
25
90
AA
A0
80
90
AA
A0
90
AA
A0
A0
90
I n f o r m a t i o n
and
S71WS-Nx0 Based MCPs
77/00
0...01
Addr
2AA
2AA
2AA
2AA
2AA
XX
XX
SA
XX
XX
XX
SA
SA
XX
00
00
00
11.2
Second
for
PWD[0-3]
PWD1
Data
data
55
00
55
03
00
55
00
30
00
55
00
00
55
00
01
00
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20.
PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit
combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If
protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,
DQ2 = 1.
8.
9.
10. See
11. “All PPB Erase” command pre-programs all PPBs before erasure
12. The second cycle address for the lock register program operation
[BA]555
[BA]555
[BA]555
0...02
Addr
555
555
Entire two bus-cycle sequence must be entered for each portion
of the password.
Full address range is required for reading password.
to prevent over-erasure.
is 77 for S29WS256N; however, for WS128N this address is 00.
00
Third
Bus Cycles (Notes 1–4)
Figure 11.2
PWD2 0...03 PWD3
PWD0
Data
40
60
C0
50
E0
Addr
01
Fourth
for details.
PWD1
Data Addr
02
Fifth
PWD2
Data
Addr
03
Sixth
PWD3
Data
Addr Data
00
Seventh
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