h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 102

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 4 Exception Handling
4.3.2
If an interrupt is accepted immediately after a reset and before the stack pointer (SP) is initialized,
the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all
interrupt requests, including NMI, are disabled immediately after a reset exception handling is
executed. Since the first instruction of a program is always executed immediately after the reset,
make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3
After reset release, MSTPCRA to MSTPCRA are initialized to H'3F, H'FF, and H'FF, and
B'11xxxxxx respectively, and all modules except the DTC enter module stop mode. Consequently,
on-chip peripheral module registers cannot be read or written to. Register reading and writing is
enabled when the module stop mode is cancelled.
Note: The initial values of bits 5 to 0 in MSTPCRD are undefined.
4.4
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt mask bit in CCR. Table 4.3
shows the states of CCR and EXR after execution of trace exception handling. Trace mode is
cancelled by clearing the T bit in EXR to 0 with the trace exception handling. The T bit saved on
the stack retains its value of 1, and when control is returned from the trace exception handling
routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out
after execution of the RTE instruction.
Interrupts are accepted even within the trace exception handling routine.
Rev. 2.00 Dec. 05, 2005 Page 64 of 724
REJ09B0200-0200
Interrupts after Reset
State of On-Chip Peripheral Modules after Reset Release
Traces