h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 137

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

6.3.5
While the break interrupt enable bit is set to 1, instruction execution is one state later than usual.
• For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip
• When break interrupt by instruction fetch is set, the set address indicates on-chip ROM or
• When break interrupt by instruction fetch is set and a break interrupt is generated, if the
• When break interrupt by instruction fetch is set and a break interrupt is generated, if the
ROM or RAM.
RAM space, and that address is used for data access, the instruction will be one state later than
in normal operation.
executing instruction immediately preceding the set instruction has one of the addressing
modes shown below, and that address indicates on-chip ROM or RAM, the instruction will be
one state later than in normal operation.
Addressing modes: @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24,
@aa:32, @(d:8,PC), @(d:16,PC), @@aa:8
executing instruction immediately preceding the set instruction is NOP or SLEEP, or has
#xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the
instruction will be one state later than in normal operation.
When Instruction Execution Is Delayed by One State
Rev. 2.00 Dec. 05, 2005 Page 99 of 724
Section 6 PC Break Controller (PBC)
REJ09B0200-0200