h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 620

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 21 Power-Down Modes
21.4
Software Standby Mode
When the SLEEP instruction is executed when the SSBY bit in SBYCR = 1, the LSON bit in
LPWRCR = 0, and the PSS bit in TCSR (WDT1) = 0, a transition is made to software standby
mode. In this mode, the CPU, on-chip peripheral modules, and oscillator all stop. However, the
contents of the CPU internal registers and on-chip RAM data, the states of on-chip peripheral
modules other than the SCI, A/D converter, motor control PWM, and HCAN, and the states of I/O
ports are retained. The address bus and bus control signals are placed in the high-impedance state.
Software standby mode is canceled by an external interrupt (NMI and IRQ5 to IRQ0 pins), or
signals at the RES pin or STBY pin.
When an NMI or IRQ5 to IRQ0 interrupt request signal is input, clock oscillation starts, and after
the time set in bits STS2 to STS0 in SBYCR has elapsed, stable clocks are supplied to the entire
chip, software standby mode is canceled, and interrupt exception handling is started.
When canceling software standby mode with an IRQ5 to IRQ0 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ5 to IRQ0 is
generated. Software standby mode cannot be canceled if the interrupt has been masked on the
CPU side or has been designated as a DTC activation source.
When the RES pin is driven low, clock oscillation starts. At the same time as clock oscillation
starts, the clock is supplied to the entire chip. Note that the RES pin must be held low until clock
oscillation stabilizes. When the RES pin is driven high, the CPU begins reset exception handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 21.3 shows an example in which a transition is made to software standby mode at a falling
edge of the NMI pin, and software standby mode is canceled at a rising edge of the NMI pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then canceled at the rising edge of the NMI pin.
Rev. 2.00 Dec. 05, 2005 Page 582 of 724
REJ09B0200-0200