h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 752

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h8s-2649

Manufacturer Part Number
h8s-2649
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Rev. 2.00 Dec. 05, 2005 Page 714 of 724
REJ09B0200-0200
Item
Figure 16.8 Disabling
Buffer Transfer
Section 17 LCD
Controller/Driver
17.1 Features
Figure 17.1 Block
Diagram of LCD
Controller/Driver
17.3.2 LCD Control
Register (LCR)
Table 17.4 Frame
Frequency Selection
Section 19 ROM
19.6.1 Boot Mode
Table 19.5 System Clock
Frequencies for which
Automatic Adjustment of
LSI Bit Rate is Possible
19.7 Flash Memory
Emulation in RAM
Page
507
510
516
542,
543
544
547
Revision (See Manual for Details)
Amended
Amended
Amended
Amended
2. SCI_1 should be set to asynchronous mode, and the
5. In boot mode, a part of the on-chip RAM area is used by the
Amended
Amended
1. The RAM area to be overlapped is fixed at a 4-kbyte area in
Host Bit Rate
19,200 bps
9,600 bps
4,800 bps
Operating Clock
φ/8
φ/16
transfer format as follows: 8-bit data, 1 stop bit, and no
parity.
boot program. The area H'FFE800 to H'FFEFBF is the area
to which the …
the range H'FFD800 to H'FFE7FF.
PWBTCR
Disabled: 1
Enabled: 0
φ/8 to φ/2048
Disabled
φw
Frame Frequency*
φ = 20 MHz
4880 Hz
2440 Hz
System Clock Frequency Range
of this LSI
20 MHz
8 to 20 MHz
4 to 20 MHz
CL2
1
Enabled

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