h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 623

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 21 Power-Down Modes
21.6
Watch Mode
When the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit
in SBYCR = 1, the DTON bit in LPWRCR = 0, and the PSS bit in TCSR (WDT1) = 1, CPU
operation shifts to watch mode.
In watch mode, the CPU stops and peripheral modules other than WDT1 also stop. The contents
of the CPU internal registers and on-chip RAM data, the states of on-chip peripheral modules
other than the SCI, A/D converter, motor control PWM, and HCAN, and the states of I/O ports are
retained.
Watch mode is canceled by any interrupt (WOVI1 interrupt, NMI pin, or IRQ5 to IRQ0 pins), or
signals at the RES or STBY pin.
When an interrupt occurs, watch mode is canceled and a transition is made to high-speed mode or
medium-speed mode when the LSON bit in LPWRCR = 0 or to subactive mode when the LSON
bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to the entire LSI
and interrupt exception handling starts after the time set in the STS2 to STS0 bits of SBYCR has
elapsed. For an IRQ5 to IRQ0 interrupt, watch mode is not canceled if the corresponding enable
bit has been cleared to 0. For an interrupt from an on-chip peripheral module, if the interrupt
enable register has been set to disable the reception of that interrupt or is masked by the CPU,
watch mode is not canceled.
For the setting of the oscillation stabilization time when making a transition from watch mode to
high-speed mode, see table 21.3.
For canceling watch mode by the RES pin, see section 21.4, Software Standby Mode.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Rev. 2.00 Dec. 05, 2005 Page 585 of 724
REJ09B0200-0200