h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 134

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 PC Break Controller (PBC)
6.2.4
BCRB is the channel B break control register. The bit configuration is the same as for BCRA.
6.3
The operation flow from break condition setting to PC break interrupt exception handling is
shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt
Due to Data Access, taking the example of channel A.
6.3.1
1. Set the break address in BARA.
2. Set the break conditions in BCR.
3. When the instruction at the set address is fetched, a PC break request is generated immediately
4. After priority determination by the interrupt controller, PC break interrupt exception handling
Rev. 2.00 Dec. 05, 2005 Page 96 of 724
REJ09B0200-0200
Bit
2
1
0
For a PC break caused by an instruction fetch, set the address of the first instruction byte as the
break address.
Set bit 6 (CDA) to 0 to select the CPU because the bus master must be the CPU for a PC break
caused by an instruction fetch. Set the address bits to be masked to bits 3 to 5 (BAMA0 to
BAMA2). Set bits 1 and 2 (CSELA0 and CSELA1) to 00 to specify an instruction fetch as the
break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.
before execution of the fetched instruction, and the condition match flag (CMFA) is set.
is started.
Bit Name
CSELA1
CSELA0
BIEA
Break Control Register B (BCRB)
Operation
PC Break Interrupt Due to Instruction Fetch
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Break Condition Select A
Selects break condition of channel A.
00: Instruction fetch is used as break condition
01: Data read cycle is used as break condition
10: Data write cycle is used as break condition
11: Data read/write cycle is used as break condition
Break Interrupt Enable A
When this bit is 1, the PC break interrupt request of
channel A is enabled.