h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 170

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Bus Controller (BSC)
Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system's load conditions, the RD signal may lag behind the CS signal (generated outside the LSI).
An example is shown in figure 7.18. In this case, with the setting for no idle cycle insertion (a),
there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS
signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD
and CS signals. In the initial state after reset release, idle cycle insertion (b) is set.
7.7.2
Table 7.4 shows the pin states in an idle cycle.
Table 7.4
Rev. 2.00 Dec. 05, 2005 Page 132 of 724
REJ09B0200-0200
Pins
A23 to A0
D15 to D0
AS
RD
HWR, LWR
CS* (area A)
Address bus
Note: * The CS signal is generated outside the LSI.
Pin States in Idle Cycle
Pin States in Idle Cycle
Figure 7.18 Relationship between Chip Select (CS) and Read (RD)
RD
Overlap period between CS (area B)
and RD may occur
φ
(a) No idle cycle insertion
T
(ICIS1 = 0)
1
Bus cycle A
T
2
Pin State
Contents of following bus cycle
High impedance
High
High
High
T
3
Bus cycle B
T
1
T
2
CS* (area A)
CS* (area B)
Address bus
RD
φ
T
(b) Idle cycle insertion
1
Bus cycle A
(ICIS1 = 1, initial value)
T
2
T
3
Idle cycle
T
i
Bus cycle B
T
1
T
2