h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 35

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Table 10.19
Table 10.20
Table 10.21
Table 10.22
Table 10.23
Table 10.24
Table 10.25
Table 10.26
Table 10.27
Table 10.28
Table 10.29
Table 10.30
Table 10.31
Table 10.32
Table 10.33
Table 10.34
Table 10.35
Table 10.36
Section 11 Programmable Pulse Generator (PPG)
Table 11.1
Section 12 Watchdog Timer (WDT)
Table 12.1
Section 13 Serial Communication Interface (SCI)
Table 13.1
Table 13.2
Table 13.3
Table 13.3
Table 13.3
Table 13.4
Table 13.5
Table 13.6
Table 13.7
Table 13.8
Table 13.9
Table 13.10
Table 13.11
Table 13.12
Pin Configuration.................................................................................................. 317
WDT Interrupt Sources......................................................................................... 346
Pin Configuration.................................................................................................. 353
The Relationships between The N Setting in BRR and Bit Rate B ...................... 366
BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ........................... 367
BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ........................... 368
BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ........................... 369
Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 369
Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 370
BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 371
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 371
Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(When n = 0 and S = 372)..................................................................................... 372
Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372)...................................................................................................... 372
TIOR_5 (Channel 5) ......................................................................................... 252
TIORH_0 (Channel 0) ...................................................................................... 253
TIORL_0 (Channel 0)....................................................................................... 254
TIOR_1 (Channel 1) ......................................................................................... 255
TIOR_2 (Channel 2) ......................................................................................... 256
TIORH_3 (Channel 3) ...................................................................................... 257
TIORL_3 (Channel 3)....................................................................................... 258
TIOR_4 (Channel 4) ......................................................................................... 259
TIOR_5 (Channel 5) ......................................................................................... 260
Register Combinations in Buffer Operation ..................................................... 276
Cascaded Combinations.................................................................................... 280
PWM Output Registers and Output Pins .......................................................... 283
Phase Counting Mode Clock Input Pins ........................................................... 287
Up/Down-Count Conditions in Phase Counting Mode 1.................................. 288
Up/Down-Count Conditions in Phase Counting Mode 2.................................. 289
Up/Down-Count Conditions in Phase Counting Mode 3.................................. 290
Up/Down-Count Conditions in Phase Counting Mode 4.................................. 291
TPU Interrupts .................................................................................................. 294
Serial Transfer Formats (Asynchronous Mode)................................................ 374
SSR Status Flags and Receive Data Handling .................................................. 381
SCI Interrupt Sources........................................................................................ 412
Rev. 2.00 Dec. 05, 2005 Page xxxv of xxxviii