h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 56

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 2 CPU
• Higher speed
2.2
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space. The mode is selected by the mode pins.
2.2.1
The exception vector table and stack have the same structure as in the H8/300 CPU.
• Address Space
• Extended Registers (En)
• Instruction Set
• Exception Vector Table and Memory Indirect Branch Addresses
Rev. 2.00 Dec. 05, 2005 Page 18 of 724
REJ09B0200-0200
 Basic instructions execute twice as fast.
Linear access to a 64-kbyte maximum address space is provided.
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even
when the corresponding general register (Rn) is used as an address register. If the general
register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or
post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding
extended register (En) will be affected.
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
In normal mode the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table structure in normal mode is
shown in figure 2.1. For details of the exception vector table, see section 4, Exception
Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode the operand is a 16-bit word operand,
providing a 16-bit branch address. Branch addresses can be stored in the area from H'0000 to
H'00FF. Note that the first part of this range is also used for the exception vector table.
CPU Operating Modes
Normal Mode