CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 107

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

The following is the sequence of operation for a single mixed-width Search command (also refer to Subsection 6.2, “Command
Bus Parameters,” on page 50).
Note. For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both cycles A and B. Also, the
even and odd pairs of GMRs selected for the comparison must be programmed with the same value. For 144-bit, 288-bit or 576-
bit searches, each 72-bit presented on each cycle A and B will together form the 144-bit or 288-bit or 576-bit search key
respectively.
When an N-bit search key, K, is presented on the DQ bus, the entire table of N-bit entries is compared to the search key using
the GMR and local mask bits. The GMR is selected by the GMR Index in the command’s cycle A. K is also stored in both even
and odd comparand register pairs (selected by the comparand register index in command cycle B). K is compared with each entry
in the table, starting at location 0. A matching entry that satisfies the Soft Priority and Mini-Key scheme (for Enhanced Mode) will
be the winning entry, and its location address L will be driven as part of the SRAM address on the SADR[N:0] lines (see
Section 6.7, “SRAM PIO Access,” on page 121), N = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. Note. The
Learn command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than
one block.
For up to 31 devices in the table (TLSZ = 10 (binary)), Search latency is 6 from command to SRAM access cycle. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 6-5.
6.5.9
This subsection will cover mixed searches (×72, ×144, and ×288) with tables of different widths (×72, ×144, ×288) when Multi-
Search is enabled. The sample operation shown is for 8-device-cascade, with devices 0 and 1 containing x72 tables (NES = 00
(binary) in all blocks), devices 2 and 3 containing x144 tables (NES = 01 (binary) in all blocks), and devices 4 to 7 containing x288
tables (NES = 10 (binary) in all blocks). The following figures show three sequential searches: first, a 72-bit Search on a ×72-
configured table; a 144-bit Search on a ×144-configured table; and a 288-bit Search on a ×288-configured table that each results
in a hit.
The hardware connection of the 8 cascaded devices is shown in Figure 6-19. A graphical representation of the tables is shown
in Figure 6-51 using CYNSE10512s as an example.
Note:
Document #: 38-02069 Rev. *F
• Cycle A:
• Cycle B:
• When MultiSearch is enabled, the maximum number of devices that can be cascaded is 8 if CLK2x is less than or equal to
• All eight devices must be programmed with the same values for TLZ (“01” (binary)) and HLAT (“000” (binary) in this example).
200 MHz. The number of devices will be 4 if CLK2x operates above 200 MHz but up to 266 MHz.
Only the last device in the table must be programmed with LRAM = 1 (binary) and LDEV = 1 (binary) (device 7 in this case).
All other upstream devices must be programmed with LRAM = 0 (binary) and LDEV = 0 (binary) (devices 0 through 6 in this case).
— Command Bus: The host ASIC drives CMDV HIGH and applies Search command CMD[1:0] = “10” (binary). The CMD[2]
— DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with the 72-bit data to be compared.
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10” (binary).
— DQ Bus: The DQ[71:0] continues to carry the search key to be compared.
Devices 0 and 1, 256K total entries in each array
Devices 2 and 3, 128K total entries in each array
and CMD[9] signals must be driven to logic 0 for the 72-bit search, but for 144-bit search, CMD[9] = 1 and CMD [2] = 0.
For 288-bit search, CMD[9] is don’t care, whereas CMD[2] = 1 for the first “A” cycle and 0 for the last “A” cycle.
{CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6]
signals must be driven with the same bits that will be driven on SADR[25:23] for CYNSE10512, SADR[24:22] for
CYNSE10256, SADR[23:21] for CYNSE10128 by this device if it has a hit.
CMD[5:2] must now be driven by the index of the comparand register pair for storing the search key presented on the DQ
bus during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the
address of the matching entry and hit flag (see page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
Devices 4 to 7, 128K total entries in each array
Mixed-size Multi Searches with 8 Devices on Tables Configured with Different Widths
Figure 6-51. Multiwidth Configurations Example for MultiSearch with CYNSE10512s
CONFIDENTIAL
PRELIMINARY
72
Array 0
144
288
NES = 00
NES = 01
NES = 10
72
144
Array 1
288
CYNSE10512
CYNSE10256
CYNSE10128
Page 107 of 153
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