CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 55

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Figure 6-4 illustrates the timing diagram for the burst Write to the data or mask array.
Burst Write operation sequence:
The Ayama 10000 device writes the data on the DQ[71:0] bus only to the subfield that has the corresponding mask bit set to 1
in the GMR specified by the index supplied in cycle 1 {CMD[10],CMD[5:3]}. The Ayama 10000 device drives the EOT signal LOW
from cycle 3 to cycle n; the Ayama 10000 device drives the EOT signal HIGH in cycle n + 1 (n is specified in the BLEN field of
the WBURREG).
At the termination of cycle n + 2, the Ayama 10000 device floats the EOT signal to a three-state operation and the next instruction
can be issued.
6.4.3
In order to write the Data or Mask array faster for initialization, testing, or diagnostics, the user can issue a Parallel Write command.
Parallel Write allows the user to specify one address and write multiple locations in the Core with the same data. Parallel Write
only works with Direct addressing. If Indirect addressing is used, the operation will result in No-Operation. Parallel Write can also
be done in burst operation.
In Non-Enhanced Mode, address bits DQ[10:1] specify which location to perform parallel write. DQ[17:11] defines a set of
partitions, all of which write two x72 entries (DQ[0] is ignored). For Ayama 10512, this corresponds to 64 parallel locations (32
8Kx72 partitions, 2 locations per partition).
In Enhanced Mode, address bits DQ[10:0] specify the location within a block. Parallel write only occurs on those blocks which
match the Mini-Key(s) selected by the GMR field. For Ayama 10512, this corresponds to 128 parallel locations (128 blocks, 1
location per block).
Document #: 38-02069 Rev. *F
• Cycle 1A: The host ASIC applies the Write instruction to CMD[1:0] (CMD[2] = 1) using CMDV = 1, and the address supplied
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1, and the address
• Cycle 2: The host ASIC drives the DQ[71:0] with the data to be written to the data or mask array location of the selected device.
• Cycles 3 to n + 1: The host ASIC drives the DQ[71:0] with the data to be written to the next data or mask array location of the
• Cycle n + 2: The Ayama 10000 device drives the EOT signal LOW.
on the DQ bus. The host ASIC also supplies the GMR index to mask the Write to the data or mask array locations in {CMD[10],
CMD[5:3]}. The host ASIC sets CMD[9] to 0 for the normal Write.
supplied on the DQ bus. The host ASIC continues to supply the GMR index to mask the Write to the data or mask array
locations in {CMD[10], CMD[5:3]}. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21] lines. It selects
all devices when DQ[25:21] = 11111.
The Ayama 10000 device writes the data from the DQ[71:0] bus only to the subfield with the corresponding mask bit set to 1
in the GMR that is specified by the index {CMD[10],CMD[5:3]} supplied in cycle 1.
selected device (addressed by the auto-increment ADR field of the WBURREG register).
Parallel Write
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
CMDV
EOT
DQ
Figure 6-4. Burst Write of the Data and Mask Arrays (BLEN = 4)
Address
cycle
A
Write
CONFIDENTIAL
1
PRELIMINARY
B
cycle
2
Data0 Data1 Data2
cycle
3
cycle
4
cycle
5
Data3
cycle
6
0
CYNSE10512
CYNSE10256
CYNSE10128
DQ should be
driven to zero in
this cycle
Page 55 of 153
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