CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 2

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

1.0 FEATURES .................................................................................................................................... 10
2.0 OVERVIEW .................................................................................................................................... 11
3.0 DEVICE ARCHITECTURE OVERVIEW ......................................................................................... 13
4.0 SIGNALS DESCRIPTION .............................................................................................................. 15
5.0 FUNCTIONAL DESCRIPTION ....................................................................................................... 18
Document #: 38-02069 Rev. *F
3.1 Data Array, Mask Array and Table Widths ................................................................................ 13
3.2 Data and Mask Addressing ....................................................................................................... 14
3.3 Successful Search and Multiple Match Arbitration .................................................................... 14
5.1 Modes of Operation .................................................................................................................. 18
5.2 I/O Interfaces ............................................................................................................................ 23
5.3 Output Signals Default Driver/Last Device Designation (LRAM and LDEV) ............................. 25
5.4 Registers ................................................................................................................................... 25
5.5 Multi-Hit Description .................................................................................................................. 41
5.6 Clocks ....................................................................................................................................... 42
5.7 Phase-Locked Loop .................................................................................................................. 43
5.8 Pipeline Latency ........................................................................................................................ 43
5.9 DQ Bus Encoding of Ayama 10000 Address Space ................................................................. 43
5.1.1 Non-Enhanced Mode ...................................................................................................................... 18
5.1.2 Enhanced Mode .............................................................................................................................. 18
5.1.2.1 Mini-Key ........................................................................................................................................................ 19
5.1.2.2 Soft Priority ................................................................................................................................................... 19
5.1.2.3 Parity ............................................................................................................................................................. 20
5.1.2.4 MultiSearch ................................................................................................................................................... 22
5.1.2.5 Enhanced Learn Operation .......................................................................................................................... 23
5.2.1 ASIC Interface ................................................................................................................................. 24
5.2.2 SRAM Interface ............................................................................................................................... 24
5.2.3 Cascade Interface ........................................................................................................................... 24
5.4.1 Comparand Register (CMPR) ......................................................................................................... 26
5.4.2 Global Mask Register (GMR) .......................................................................................................... 26
5.4.3 Search Successful Register (SSR) ................................................................................................. 27
5.4.4 Command Register (COMMAND) ................................................................................................... 28
5.4.5 Information Register (INFO) ............................................................................................................ 30
5.4.6 Read Burst Address Register (RBURREG) .................................................................................... 30
5.4.7 Write Burst Address Register (WBURREG) .................................................................................... 31
5.4.8 Next-free Address Register (NFA) .................................................................................................. 31
5.4.9 Configuration Register (CONFIG) ................................................................................................... 32
5.4.10 Hardware Register (HARDWARE) ................................................................................................ 33
5.4.11 Parity Control Register (PARITY) .................................................................................................. 34
5.4.12 Control Register (CPR[0:15]) ........................................................................................................ 35
5.4.13 Search Result Register (SRR[15:0]) ............................................................................................. 36
5.4.14 Block Mini-Key Register (BMR) ..................................................................................................... 37
5.4.15 Block Priority Register (BPR) ........................................................................................................ 38
5.4.16 Block Parity Register (BPAR) ........................................................................................................ 39
5.4.17 Block NFA Register (BNFA) .......................................................................................................... 39
5.4.18 Block Priority Register Aliases (BPRA) ......................................................................................... 40
5.9.1 Addressing the Data Array, Mask Array and External SRAM ......................................................... 44
5.9.2 Addressing the Internal Registers ................................................................................................... 45
TABLE OF CONTENTS
CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Page 2 of 153
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